Spansion has developed the first family of products based on the new Spansion® HyperBus™ interface, Spansion HyperFlash™ NOR Memory devices. The family features read throughput of up to 333 megabytes per second—more than five times faster than ordinary Quad SPI flash currently available with one-third the number of pins of parallel NOR flash.
Spansion HyperFlash Memory family will offer 3V and 1.8V power-supply versions and initially include three densities: 128Mb, 256Mb and 512Mb, with the 512Mb devices sampling in the second quarter of 2014. HyperFlash memories will be available in a space-saving 8x6mm ball grid array (BGA) package. Spansion HyperFlash Memory devices provide a migration path—from single Quad SPI to Dual Quad SPI to HyperFlash Memory—allowing system applications to be scaled to different levels of flash performance when paired with compatible controllers, giving OEMs the ability to offer different product models with a single design.
Spansion HyperBus Interface Enables Fast, Efficient Applications
Spansion® HyperBus™ Interface is a breakthrough that dramatically improves read performance while reducing the number of pins. The efficient 12-pin Spansion HyperBus Interface consists of an 8-pin address/data bus, a differential clock (2 signals), one Chip Select and a Read Data Strobe for the controller, reducing the overall cost of the system. The Spansion HyperBus Interface is being implemented broadly by leading system-on-chip (SoC) manufacturers.