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There are several categories of simulation models and CAD models available for Spansion® Flash memory devices:

• For digital circuit simulation and timing verification, the most common model formats are VHDL and Verilog. They replicate command inputs and outputs as found in the device datasheet.
• For signal integrity tests and transition response, the preferred model is IBIS format.

VHDL/Verilog Models – Cost-Free, Industry Standard

Demonstrating a strong commitment to open industry standards, Spansion has developed a comprehensive set of VHDL and Verilog behavioral simulation models for our Flash memory products. Spansion's VHDL and Verilog simulation models are compatible with virtually any CAD modeling environment.

VHDL/Verilog Simulation Models from Denali Software

Denali licenses simulation models for Spansion Flash devices are compatible with all commercial Verilog, SystemVerilog, VHDL, C/C++ simulators, and all popular testbench languages such as SystemC, C/C++, OpenVERA and Specman e. The models are available now from Denali at: www.eMemory.com/Spansion-FLASH

Denali models include complete BFM, assertion libraries and automatic monitoring of device specific features, function and timing. For more information, email info@denali.com

IBIS Models – Cost-Free, Industry Standard

IBIS (I/O Buffer Information Specification) is a behavioral description of the I/O buffers and package characteristics of a semiconductor device. A consortium of semiconductor companies developed the IBIS model format for the express purpose of giving customers the data they needed without sharing proprietary HSPICE models. Use IBIS to check/verify signal integrity, EMI, and transition response.