Spansion® takes NOR flash lead

Cedric Paillard, EE Times (05/02/2005 9:00 AM EDT)

Source: http://www.eetimes.com/showArticle.jhtml?articleID=161601585

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Spansion® LLC is currently ranked first in the NOR market and second in the overall flash market. Intel Corp., the only other major NOR vendor, is fourth in the overall market and second to Spansion in NOR. The dynamics of the flash market are changing, with a blurring of NAND and NOR technologies and the announcement or delivery of converged offerings, including Samsung's OneNAND and Spansion's ORNAND™. Intel is the only flash vendor following an exclusive NOR strategy with no NAND offering.

Most of Intel's design wins are in cell phones. As cell phones converge into mobile entertainment devices with vast storage requirements ideally suited to NAND, many questions remain, including the longevity of a NOR-only strategy and Intel's ability to compete in a commoditizing market. Current cell phone/handset design-win information from Semiconductor Insights (SI) shows Intel with 30 flash design wins and Spansion with 28, on a base of 55 handsets at the end of March. The deciding factor for market dominance in the quarters ahead will likely come to down to cost. With rumored delays in Intel's 90-nanometer flash program, Spansion appears to be pushing the process technology envelope for NOR with its 110-nm MirrorBit® flash. This could explain Intel's recent decision to seek alternative flash opportunities in the embedded market.

Both Intel and Spansion use floating-gate-based flash programs, but they each use a different approach for flash that stores multiple bits in each cell. In 2002, the first memory featuring nitride-based trapped-charge technology using multibit-per-cell (MBC) MirrorBit NOR flash technology was introduced by AMD-Fujitsu (now Spansion). It featured mature 0.23-micron technology.

Intel, on the other hand, has been using a floating-gate-based multilevel-per-cell technology known as StrataFlash, now deployed in its fourth generation in a 0.13-micron process.

Intel has repeatedly announced its 90-nm StrataFlash program over the past year, though its commercial production availability remains unknown. In 2004, Spansion brought production 110-nm-based MirrorBit devices to market with monolithic products up to 512 Mbits in density. The 512-Mbit, 110-nm product showed memory array efficiency and die utilization exceeding those of the 130-nm Intel L18 StrataFlash. The 256-Mbit, 1.8-volt product from Spansion has metrics comparable to the 130-nm Intel L18, as analyzed by SI. The key cost structure parameters are summarized in the table.

Spansion has moved ahead of Intel with respect to die utilization for its 3-V, 512-Mbit device and has metrics comparable to Intel's for its 1.8-V, 256-Mbit part, which is optimized for performance with read-while-write capability. For both Spansion parts, the key metric of cell size is approximately 23 percent superior to that of the Intel L18.

One of the reasons for the die efficiency rating difference between Spansion's 256-Mbit and 512-Mbit parts is that in the 256-Mbit product, a larger proportion of the device is used for the memory peripherals and the nonarray areas of the die to optimize performance. The 512-Mbit device has a higher die efficiency rating. It is achieved by amortizing a larger array over a relatively smaller proportion of nonmemory periphery. SI also noted a more efficient routing in the 512-Mbit device compared with the 256-Mbit device.

Cost vs. performance
Spansion claims that its 1.8-V, 256-Mbit MirrorBit device outperforms any multilayer-cell, multibit-cell or conventional floating-gate flash on the market today. The 256-Mbit part is rated at 66 MHz and above vs. 54 MHz for others today. Spansion uses the same cell for both devices, but the 1.8-V, 256-Mbit part has lots of optimized peripheral circuits for performance gains.

One of the purported advantages of trapped-charge technology was supposed to be the superior performance due to simpler sensing circuits. For the moment, Spansion seems to have brought this benefit to market. SI will perform further analysis on some of these claims over the next quarter.

Process technology
A major benefit of MirrorBit technology is the trapped-charge architecture, which uses no floating gate. This means that separate poly is not required for floating-gate and control-gate layers. A cost savings is thus gained by Spansion in using one poly layer vs. Intel using two poly layers for its floating-gate implementation.

At its 2003 Analyst Day, Spansion maintained that its wafer cost, yield and smaller die size for a 128-Mbit device in 110 nm would be about half the cost of an equivalent floating-gate device in 130 nm (using the metrics from the company's own floating-gate program). Given the die efficiency, the lower number of process mask steps and the reduced number of poly layers, this statement appears to have come to fruition.

All vendors need to be concerned by some of the advantages of nitride-based MBC technology.

By Cedric Paillard (cedricp@semiconductor.com), TECHinsights director at Semiconductor Insights (Kanata, Ontario)

In Brief

The hybrid Fujitsu-AMD venture now called Spansion is currently ranked No. 1 in the overall flash market. Intel, with its NOR-only strategy, is fourth overall and second to Spansion in NOR. To regain NOR market leadership and improve its overall position in the flash market, Intel must bring its long-awaited 90-nanometer StrataFlash to market before Spansion is able to realize its 90-nm

MirrorBit program. At Semiconductor Insights, we believe that when both vendors are at 90 nm, they will have fairly close cell sizes and cost structures.

There are some claims that nitride-based technology has higher yields than conventional floating-gate technology, which would give Spansion the edge. But the greater competitive pressure for both vendors will likely come from incorporating NAND and other memories (SRAM, PSRAM, DRAM) into multichip packages. Spansion has announced plans for a converged NAND-NOR offering known as ORNAND. For the moment, what the NAND-based implementations gain on the density front they give away in random-access time, especially when code branches and has to go off page. Spansion and Intel will have to work aggressively on write performance, however, to defend design wins for data-intensive handsets while they fight the cost battle with each other.

As in all semiconductor markets, vendors are constantly trading off among performance, power consumption, density and cost. For the moment, Spansion appears to have taken over the lead from Intel on several key metrics.