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Burst-mode and page-mode interface
Multi-Chip-Package (MCP) Solutions
S29GL256N
The S29GL512/256/128N family of devices are 3.0V single power flash memory manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256 Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a 128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers.
| Device Architecture | |
| Density | 256Mb |
| Voltage | 3 Volts |
| Interface | Page-mode |
| Process Technology | 110 nm MirrorBit® technology |
| Bus Width | x8/x16 |
| Sector Type | Uniform |
| Basic Ordering Options | |
| Initial Access Times (ns) | 90/100/110 |
| Page Mode Access Times (ns) | 25/30 |
| Package Options |
56-pin TSOP 64-ball Fortified BGA |
| Temperature Range |
-40°C to 85°C |
| Downloads | Document code | Last updated |
| s29gl-n_00_b8_e.pdf | s29gl-n_00_b8_e | May. 30, 2008 |
| S29GL128256N_A2_E.- ALT_PINOUT |
S29GL128256N_01_A2_E | Aug. 31, 2005 |
| SOMA | IBIS | VHDL & Verilog-HDL |
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s29gl256n_TSOP_18.zip s29gl256n_TSOP_3.zip s29gl256n_laa064_3.ibs s29gl256n_laa064_18.ibs s29gl256n_faa_064_i |
S29GL256N.zip S29GL256N_S.zip |
